496 search results - page 17 / 100 » Using the Temporal Logic RDL for Design Specifications |
109
click to vote
SEKE
2001
Springer
15 years 6 months ago
2001
Springer
ct 7 Applying finite-state verification techniques to software systems looks attractive because they are capable of detecting very subtle 8 defects in the logic design of these s...
153
click to vote
CDC
2010
IEEE
14 years 9 months ago
2010
IEEE
In this paper, we consider the problem of motion planning for mobile robots with nonlinear hybrid dynamics, and high-level temporal goals. We use a multi-layered synergistic framew...
DAC
2004
ACM
16 years 2 months ago
2004
ACM
The desynchronization approach combines a traditional synchronous specification style with a robust asynchronous implementation model. The main contribution of this paper is the d...
132
Voted
FPGA
2003
ACM
15 years 7 months ago
2003
ACM
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
115
click to vote
FOIKS
2006
Springer
15 years 5 months ago
2006
Springer
This paper presents a semantic foundation of temporal conceptual models used to design temporal information systems. We consider a modeling language able to express both timestampi...