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» Using the Temporal Logic RDL for Design Specifications
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KBSE
2005
IEEE
15 years 3 months ago
Properties and scopes in web model checking
We consider a formal framework for property verification of web applications using Spin model checker. Some of the web related properties concern all states of the model, while ot...
May Haydar, Sergiy Boroday, Alexandre Petrenko, Ho...
EH
1999
IEEE
351views Hardware» more  EH 1999»
15 years 2 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
ECCTD
2011
72views more  ECCTD 2011»
13 years 9 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic
ECSCW
1993
14 years 11 months ago
Design for Unanticipated Use..
: Support for work practice is better conceptualised as support for activity taking place in a multidimensional space than as prescription of temporal task sequences. The notion of...
Mike Robinson
CDC
2010
IEEE
144views Control Systems» more  CDC 2010»
14 years 4 months ago
Formal analysis of piecewise affine systems through formula-guided refinement
Abstract-- We present a computational framework for identifying a set of initial states from which all trajectories of a piecewise affine (PWA) system satisfy a Linear Temporal Log...
Boyan Yordanov, Jana Tumova, Calin Belta, Ivana Ce...