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» Using the Temporal Logic RDL for Design Specifications
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VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
15 years 10 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu
DATE
2006
IEEE
117views Hardware» more  DATE 2006»
15 years 3 months ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
SIGSOFT
2008
ACM
15 years 10 months ago
Javert: fully automatic mining of general temporal properties from dynamic traces
Program specifications are important for many tasks during software design, development, and maintenance. Among these, temporal specifications are particularly useful. They expres...
Mark Gabel, Zhendong Su
DIMACS
1996
14 years 11 months ago
Model Checking and the Mu-calculus
There is a growing recognition of the need to apply formal mathematical methods in the design of \high con dence" computing systems. Such systems operate in safety critical co...
E. Allen Emerson
CADE
2006
Springer
15 years 10 months ago
Specifying and Reasoning About Dynamic Access-Control Policies
Access-control policies have grown from simple matrices to non-trivial specifications written in sophisticated languages. The increasing complexity of these policies demands corres...
Daniel J. Dougherty, Kathi Fisler, Shriram Krishna...