496 search results - page 24 / 100 » Using the Temporal Logic RDL for Design Specifications |
103
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
PSTV
1993
14 years 11 months ago
1993
We present a new algorithm that can be used for solving the model−checking problem for linear−time temporal logic. This algorithm can be viewed as the combination of two exist...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
104
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TIME
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents the automatic extension of TERSEO to other languages, a knowledge-based system for the recognition and normalization of temporal expressions, originally develo...
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...