496 search results - page 27 / 100 » Using the Temporal Logic RDL for Design Specifications |
ICSE
2005
IEEE-ACM
15 years 9 months ago
2005
IEEE-ACM
Embedded systems are pervasive and frequently used for critical systems with time-dependent functionality. Dwyer et al. have developed qualitative specification patterns to facili...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
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VIS
2004
IEEE
15 years 11 months ago
2004
IEEE
Typically there is a high coherence in data values between neighboring time steps in an iterative scientific software simulation; this characteristic similarly contributes to a co...
SEW
2003
IEEE
15 years 3 months ago
2003
IEEE
Run-time monitoring is a lightweight verification method whereby the correctness of a programs’ execution is verified at run-time using executable specifications. This paper des...