496 search results - page 34 / 100 » Using the Temporal Logic RDL for Design Specifications |
CSEE
2000
Springer
15 years 2 months ago
2000
Springer
Accurate and complete requirements specifications are crucial for the design and implementation of high-quality software. Unfortunately, the articulation and verification of softw...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
ICRA
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper describes a set of tools that allows a developer to instrument an autonomous control system to log data at run-time and then analyze that data to verify correct program...
RE
2001
Springer
15 years 2 months ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
FDL
2006
IEEE
15 years 1 months ago
2006
IEEE
Many different system description and specification languages are used in modern design flows to emphasize different aspects like modular architecture, multibehavior, abstract act...