496 search results - page 41 / 100 » Using the Temporal Logic RDL for Design Specifications |
KBSE
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper describes the application of advanced formal modelling techniques and tools from the CADP toolset to the verification of CFS, a distributed file system kernel. After a ...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
15 years 2 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
FPL
2005
Springer
15 years 3 months ago
2005
Springer
In many industrial processes, an incorrect operation can lead to irreparable damage to people, equipment, or the environment. In order to reduce risks, the electronic control syst...
DBA
2004
2004
A Tool for Transforming Conceptual Schemas of Spatio-Temporal Databases with Multiple Representation
14 years 11 months ago
Nowadays, classical conceptual models (such as ER or UML) are used for designing database applications. These classical conceptual models usually come with associated CASE tools a...
IPPS
1998
IEEE
15 years 2 months ago
1998
IEEE
This work presents MUSE, a graphical environment for modeling interactive networked multimedia applications. Through an advanced graphic interface and a new highlevel authoring mod...