496 search results - page 50 / 100 » Using the Temporal Logic RDL for Design Specifications |
IWFM
2003
14 years 11 months ago
2003
This paper describes the derivation of a program for the propagation of information over a network, with acknowledgement (feedback) when the computation is complete. The derivatio...
FPGA
2004
ACM
15 years 1 months ago
2004
ACM
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
CAISE
2010
Springer
14 years 4 months ago
2010
Springer
Abstract. Formal specification and operational support of time constraints constitute fundamental challenges for any process-aware information system. Although temporal constraints...
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...