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» Using the Temporal Logic RDL for Design Specifications
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SP
2010
IEEE
152views Security Privacy» more  SP 2010»
14 years 7 months ago
Scalable Parametric Verification of Secure Systems: How to Verify Reference Monitors without Worrying about Data Structure Size
The security of systems such as operating systems, hypervisors, and web browsers depend critically on reference monitors to correctly enforce their desired security policy in the ...
Jason Franklin, Sagar Chaki, Anupam Datta, Arvind ...
ISQED
2002
IEEE
106views Hardware» more  ISQED 2002»
15 years 2 months ago
Trading off Reliability and Power-Consumption in Ultra-low Power Systems
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
Atul Maheshwari, Wayne Burleson, Russell Tessier
PODS
2007
ACM
109views Database» more  PODS 2007»
15 years 10 months ago
What is "next" in event processing?
Event processing systems have wide applications ranging from managing events from RFID readers to monitoring RSS feeds. Consequently, there exists much work on them in the literat...
Walker M. White, Mirek Riedewald, Johannes Gehrke,...
ICCD
1992
IEEE
84views Hardware» more  ICCD 1992»
15 years 1 months ago
Synthesis of 3D Asynchronous State Machines
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
Kenneth Y. Yun, David L. Dill, Steven M. Nowick
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 1 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja