496 search results - page 56 / 100 » Using the Temporal Logic RDL for Design Specifications |
143
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ICCAD
2009
IEEE
15 years 2 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
163
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DSVIS
2005
Springer
15 years 10 months ago
2005
Springer
Abstract. The ConcurTaskTrees (CTT) is one of the most widely used notations for task modeling, specifically tailored for user interface model-based design. The integration of CTT ...
133
Voted
ASE
2008
15 years 5 months ago
2008
Goal-oriented methods are increasingly popular for elaborating software requirements. They offer systematic support for incrementally building intentional, structural, and operati...
140
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CONSTRAINTS
2008
15 years 5 months ago
2008
We present a novel approach to automatically reformulating constraints defined as tables of allowed assignments to variables. Constraints of this form are common in a variety of se...
138
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EUROMICRO
2006
IEEE
15 years 11 months ago
2006
IEEE
This paper presents a modular modelling methodology to formulate the timing behaviour of real-time distributed component-based applications. It allows to build real-time models of...