496 search results - page 56 / 100 » Using the Temporal Logic RDL for Design Specifications |
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
DSVIS
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. The ConcurTaskTrees (CTT) is one of the most widely used notations for task modeling, specifically tailored for user interface model-based design. The integration of CTT ...
ASE
2008
14 years 10 months ago
2008
Goal-oriented methods are increasingly popular for elaborating software requirements. They offer systematic support for incrementally building intentional, structural, and operati...
CONSTRAINTS
2008
14 years 9 months ago
2008
We present a novel approach to automatically reformulating constraints defined as tables of allowed assignments to variables. Constraints of this form are common in a variety of se...
EUROMICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a modular modelling methodology to formulate the timing behaviour of real-time distributed component-based applications. It allows to build real-time models of...