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» Using the Temporal Logic RDL for Design Specifications
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AMAST
2006
Springer
15 years 1 months ago
State Space Representation for Verification of Open Systems
Abstract. When designing an open system, there might be no implementation available for certain components at verification time. For such systems, verification has to be based on a...
Irem Aktug, Dilian Gurov
CIKM
2007
Springer
15 years 4 months ago
Link analysis using time series of web graphs
Link analysis is a key technology in contemporary web search engines. Most of the previous work on link analysis only used information from one snapshot of web graph. Since commer...
Lei Yang, Lei Qi, Yan-Ping Zhao, Bin Gao, Tie-Yan ...
ENTCS
2007
130views more  ENTCS 2007»
14 years 9 months ago
Specify, Compile, Run: Hardware from PSL
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
Roderick Bloem, Stefan Galler, Barbara Jobstmann, ...
CAV
2010
Springer
227views Hardware» more  CAV 2010»
14 years 7 months ago
Breach, A Toolbox for Verification and Parameter Synthesis of Hybrid Systems
We describe Breach, a Matlab toolbox providing a coherent set of simulation-based techniques aimed at the analysis of deterministic models of hybrid dynamical systems. The primary ...
Alexandre Donzé
ACTA
2011
14 years 4 months ago
Nonatomic dual bakery algorithm with bounded tokens
A simple mutual exclusion algorithm is presented that only uses nonatomic shared variables of bounded size, and that satisfies bounded overtaking. When the shared variables behave...
Alex A. Aravind, Wim H. Hesselink