496 search results - page 66 / 100 » Using the Temporal Logic RDL for Design Specifications |
DIAGRAMS
2004
Springer
15 years 1 months ago
2004
Springer
Constraint diagrams are a diagrammatic notation which may be used to express logical constraints. They were designed to complement the Unified Modeling Language in the development ...
VSTTE
2005
Springer
15 years 3 months ago
2005
Springer
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...
BIRTHDAY
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. The error-prone process of formal specification and verification of large systems requires an efficient, evolutionary formal development approach. Development graphs have...
EKNOW
2009
14 years 7 months ago
2009
Modeling is a complex and central activity in many domains. Domain experts and designers usually work by drawing and create models from the middle-out; however, visual and middle-...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...