496 search results - page 70 / 100 » Using the Temporal Logic RDL for Design Specifications |
EKAW
1999
Springer
15 years 2 months ago
1999
Springer
: The aim of this paper is to present an approach and automated tools for designing knowledge bases describing the contents of information sources in PICSEL2 knowledgediators. We a...
FASE
2009
Springer
15 years 1 months ago
2009
Springer
This paper describes the certification of smart-card applications in the framework of Common Criteria. In this framework, a smart-card application is represented by a model of its...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
OOPSLA
2005
Springer
15 years 3 months ago
2005
Springer
Designing component-based application that meets performance requirements remains a challenging problem, and usually requires a prototype to be constructed to benchmark performanc...