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» Using the Temporal Logic RDL for Design Specifications
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ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
15 years 1 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
BMCBI
2005
169views more  BMCBI 2005»
14 years 9 months ago
MAPPER: a search engine for the computational identification of putative transcription factor binding sites in multiple genomes
Background: Cis-regulatory modules are combinations of regulatory elements occurring in close proximity to each other that control the spatial and temporal expression of genes. Th...
Voichita D. Marinescu, Isaac S. Kohane, Alberto Ri...
DAC
2004
ACM
15 years 10 months ago
Defining coverage views to improve functional coverage analysis
Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequat...
Sigal Asaf, Eitan Marcus, Avi Ziv
HT
2004
ACM
15 years 3 months ago
Automatic generation of hypertext system repositories: a model driven approach
In this paper, we present a model-driven methodology and toolset for automatic generation of hypertext system repositories. Our code generator, called Bamboo, is based on a Contai...
E. James Whitehead Jr., Guozheng Ge, Kai Pan
ATAL
2009
Springer
15 years 4 months ago
Combining fault injection and model checking to verify fault tolerance in multi-agent systems
The ability to guarantee that a system will continue to operate correctly under degraded conditions is key to the success of adopting multi-agent systems (MAS) as a paradigm for d...
Jonathan Ezekiel, Alessio Lomuscio