496 search results - page 75 / 100 » Using the Temporal Logic RDL for Design Specifications |
ICCAD
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
102
Voted
CASES
2010
ACM
14 years 7 months ago
2010
ACM
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
BCS
2008
14 years 11 months ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
TACAS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. Recent studies have demonstrated the possibility to build genetic regulatory networks that confer a desired behavior to a living organism. However, the design of these ne...
SIGSOFT
1998
ACM
15 years 1 months ago
1998
ACM
Implicit invocation SN92, GN91] has become an important architectural style for large-scale system design and evolution. This paper addresses the lack of speci cation and veri cat...