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» Using the Temporal Logic RDL for Design Specifications
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ACSAC
1999
IEEE
15 years 2 months ago
Tools to Support Secure Enterprise Computing
Secure enterprise programming is a difficult and tedious task. Programmers need tools that support t levels of abstraction and that track all the components that participate in di...
Myong H. Kang, Brian J. Eppinger, Judith N. Frosch...
DAC
2004
ACM
15 years 10 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
DAC
2002
ACM
15 years 10 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
POPL
2010
ACM
15 years 7 months ago
Counterexample-Guided Focus
The automated inference of quantified invariants is considered one of the next challenges in software verification. The question of the right precision-efficiency tradeoff for the...
Andreas Podelski, Thomas Wies
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
15 years 4 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon