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352
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VHDL
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EURODAC
1995
IEEE
314
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VHDL
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EURODAC 1995
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Procedure exlining: a new system-level specification transformation
14 years 2 months ago
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Frank Vahid
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84
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EURODAC
1995
IEEE
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Functional-level analog macromodeling with piecewise linear signals
14 years 2 months ago
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Jerzy Dabrowski
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72
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EURODAC
1995
IEEE
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A classification of design steps and their verification
14 years 2 months ago
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Wolfgang Ecker
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71
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EURODAC
1994
IEEE
272
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VHDL
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EURODAC 1994
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A transformation for integrating VHDL behavioral specification with synthesis and software generation
14 years 2 months ago
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Frank Vahid, Daniel D. Gajski, Sanjiv Narayan
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76
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EURODAC
1994
IEEE
377
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EURODAC 1994
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VHDL switch level fault simulation
14 years 2 months ago
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Christopher A. Ryan, Joseph G. Tront
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