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DATE
1997
IEEE
88views Hardware» more  DATE 1997»
15 years 1 months ago
VHDL extensions for complex transmission line simulation
This paper proposes extensions to the VHDL grammar and de nes new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, dis...
Peter Walker, Sumit Ghosh
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
15 years 1 months ago
Modeling shared variables in VHDL
A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing su...
Jan Madsen, Jens P. Brage
EURODAC
1994
IEEE
163views VHDL» more  EURODAC 1994»
15 years 1 months ago
VHDL and cyclic corrector codes
Cyclic corrector codes, or "block codes", are often used in telecommunications systems. To facilitate the design of coding/decoding circuits using this type of code, we ...
France Mendez
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
15 years 2 months ago
A VHDL Error Simulator for Functional Test Generation
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
Alessandro Fin, Franco Fummi
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
15 years 2 months ago
Parallel and Distributed VHDL Simulation
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Dragos Lungeanu, C.-J. Richard Shi