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EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
15 years 1 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
EURODAC
1994
IEEE
221views VHDL» more  EURODAC 1994»
15 years 1 months ago
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...
Juan Carlos Calderón, Enric Corominas, Jos&...
PACT
2005
Springer
15 years 3 months ago
Information Flow Analysis for VHDL
We describe a fragment of the hardware description language VHDL that is suitable for implementing the Advanced Encryption Standard algorithm. We then define an Information Flow a...
Terkel K. Tolstrup, Flemming Nielson, Hanne Riis N...
67
Voted
DATE
1999
IEEE
95views Hardware» more  DATE 1999»
15 years 1 months ago
Object-Oriented Reuse Methodology for VHDL
In the reuse domain, the necessity of finding a new, more suitable description language opposes the need to make reuse an accepted practice, and thus related to standards. This pa...
Cristina Barna, Wolfgang Rosenstiel
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
15 years 1 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng