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SAFECOMP
2000
Springer
15 years 1 months ago
Speeding-Up Fault Injection Campaigns in VHDL Models
Abstract. Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents ...
B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reo...
CODES
2003
IEEE
15 years 2 months ago
Early estimation of the size of VHDL projects
The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry. In particular, early estimatin...
William Fornaciari, Fabio Salice, Daniele Paolo Sc...
FPL
2007
Springer
142views Hardware» more  FPL 2007»
15 years 3 months ago
DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator
In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, avail...
Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georg...
DATE
1998
IEEE
107views Hardware» more  DATE 1998»
15 years 1 months ago
A Flexible Message Passing Mechanism for Objective VHDL
When defining an object-oriented extension to VHDL, the necessary message passing is one of the most complex issues and has a large impact on the whole language. This paper identi...
Wolfram Putzke-Röming, Martin Radetzki, Wolfg...
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
Design automation of self checking circuits
In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint ...
Sayed Mohammad Kia, Sri Parameswaran