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ITC
1997
IEEE
119views Hardware» more  ITC 1997»
15 years 1 months ago
Testability Analysis and ATPG on Behavioral RT-Level VHDL
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
AHS
2007
IEEE
263views Hardware» more  AHS 2007»
15 years 4 months ago
Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C
Since their invention in the 1980s, the logic density of FPGAs has increased exponentially with time. This increase of logic density first led to the development of synthesisable ...
Gildas Genest, Richard Chamberlain, Robin J. Bruce
FPL
2006
Springer
223views Hardware» more  FPL 2006»
15 years 1 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
15 years 2 months ago
Digital statistical analysis using VHDL
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
Manfred Dietrich, Uwe Eichler, Joachim Haase
62
Voted
IPPS
2006
IEEE
15 years 3 months ago
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow
Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenz...