Sciweavers

352 search results - page 19 / 71
» VHDL
Sort
View
57
Voted
JISE
1998
54views more  JISE 1998»
14 years 9 months ago
Entity Overloading for Mixed-Signal Abstraction in VHDL
C.-J. Richard Shi
EURODAC
1994
IEEE
112views VHDL» more  EURODAC 1994»
15 years 1 months ago
The use of semantic information for control of a complex routing tool
To handle increasingly complex design data, CAD tools are becoming more specialised and complex and hence, more difficult to use. This paper describes an interactive system that h...
Michael Brown, Nick Filer, Zahir Moosa
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 1 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
EURODAC
1994
IEEE
115views VHDL» more  EURODAC 1994»
15 years 1 months ago
A method for partitioning UNITY language in hardware and software
In this paper we introduce a method to partition UNITY system speci cations into software and hardware parts. This method considers di erent design possibilities and de nes cost f...
Xun Xiong, Edna Barros, Wolfgang Rosenstiel
EURODAC
1990
IEEE
74views VHDL» more  EURODAC 1990»
15 years 1 months ago
Matching system and component behaviour in MIMOLA synthesis tools
This paper discusses the selection of available components during high-level synthesis. We stress the importance of describing the behaviour of available components in some langua...
Peter Marwedel