352 search results - page 21 / 71 » VHDL |
103
Voted
CONIELECOMP
2011
IEEE
14 years 1 months ago
2011
IEEE
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
FPL
2003
Springer
15 years 2 months ago
2003
Springer
At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map fast and efficiently applications written in Matlab onto recon...
DFT
2007
IEEE
15 years 4 months ago
2007
IEEE
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...