352 search results - page 25 / 71 » VHDL |
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry ...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper addresses the problem of semantic heterogeneity between data representations with particular emphasis on CAD tool data representations. The combination of powerful mapp...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
The synthesis of electronic circuits on system level o ers the possibility to nd better locations of the A/D interfaces and to determine parameters like clock rates and bit widths...