352 search results - page 30 / 71 » VHDL |
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven ...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...