Sciweavers

352 search results - page 32 / 71
» VHDL
Sort
View
EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
15 years 1 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
15 years 1 months ago
Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics
Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...
E. Leroux, Flavio G. Canavero, G. Vecchi
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 1 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
15 years 1 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
15 years 1 months ago
Semi-dynamic scheduling of synchronization-mechanisms
This paper presents a novel approach to scheduling of hardware supported synchronization operations. The optimization goal is to minimize the interation time of processes and thus...
Wolfgang Ecker