352 search results - page 36 / 71 » VHDL |
ASPDAC
2000
ACM
15 years 2 months ago
2000
ACM
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
RSP
1999
IEEE
15 years 1 months ago
1999
IEEE
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...