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EURODAC
1995
IEEE
202views VHDL» more  EURODAC 1995»
15 years 1 months ago
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems...
Santhanam Srinivasan, Niraj K. Jha
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
15 years 1 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
EURODAC
1995
IEEE
101views VHDL» more  EURODAC 1995»
15 years 1 months ago
Exploiting power-up delay for sequential optimization
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
ICIP
2002
IEEE
15 years 11 months ago
Benchmarking and hardware implementation of JPEG-LS
The JPEG-LS algorithm is one of the recently designated standards for lossless compression of grayscale and color images. In this paper, simulation results for lossless and near l...
Andreas E. Savakis, Michael D. Piorun
DSD
2008
IEEE
79views Hardware» more  DSD 2008»
15 years 4 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
Martin Straka, Zdenek Kotásek, Jan Winter