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ETS
2006
IEEE
113views Hardware» more  ETS 2006»
15 years 3 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
15 years 3 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
MSE
2005
IEEE
118views Hardware» more  MSE 2005»
15 years 3 months ago
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory
This paper describes our experience to date and current plans for a senior-level microelectronics laboratory course on hardware/software codesign. The course utilizes an open-sour...
Roger D. Chamberlain, John W. Lockwood, Saurabh Ga...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 3 months ago
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform
In this paper, the EX-VPR tool, which used for architecture level exploration, is presented. This tool belongs to an integrated framework (MEANDER) for mapping applications into a...
K. Siozios, Konstantinos Tatas, George Koutroumpez...
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FPL
2005
Springer
79views Hardware» more  FPL 2005»
15 years 3 months ago
FPGA-based implementation and comparison of recursive and iterative algorithms
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
Valery Sklyarov, Iouliia Skliarova, Bruno Figueire...