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ARITH
2003
IEEE
15 years 3 months ago
Some Optimizations of Hardware Multiplication by Constant Matrices
This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant m...
Nicolas Boullis, Arnaud Tisserand
73
Voted
ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
15 years 3 months ago
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems
The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and h...
Dimitrios Soudris, K. Sgouropoulos, Konstantinos T...
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
15 years 3 months ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang
GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
15 years 2 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
59
Voted
IEAAIE
1999
Springer
15 years 1 months ago
New Directions in Debugging Hardware Designs
This paper introduces a new approach in the debugging of hardware designs. The design is given as a VHDL program and converted in a component connection model. The conversion is si...
Franz Wotawa