352 search results - page 40 / 71 » VHDL |
62
Voted
DATE
1997
IEEE
15 years 1 months ago
1997
IEEE
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
73
Voted
DATE
1997
IEEE
15 years 1 months ago
1997
IEEE
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
FCCM
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
FPL
2006
Springer
15 years 1 months ago
2006
Springer
An intermediate representation (IR) is a central structure around which tools such as compilers and synthesis tools are built. In this paper we propose such an IR specifically des...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...