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ICIP
1998
IEEE
16 years 1 months ago
Hardware Architecture for Optical Flow Estimation in Real Time
Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work a specific a...
Aitzol Zuloaga, José Luis Martín, Jo...
ICPR
2004
IEEE
16 years 28 days ago
An FPGA-Based Architecture for Real Time Image Feature Extraction
We propose a novel FPGA-based architecture for the extraction of four texture features using Gray Level Cooccurrence Matrix (GLCM) analysis. These features are angular second mome...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
DAC
2002
ACM
16 years 24 days ago
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...
Mike Bartley, Darren Galpin, Tim Blackmore
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
16 years 6 days ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
ARC
2009
Springer
181views Hardware» more  ARC 2009»
15 years 6 months ago
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers
Abstract. In this paper, we present CCProc, a flexible cryptography coprocessor for symmetric-key algorithms. Based on an extensive analysis of many symmetric-key ciphers, includi...
Dimitris Theodoropoulos, Alexandros Siskos, Dionis...