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DSD
2002
IEEE
88views Hardware» more  DSD 2002»
15 years 2 months ago
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
Omar Mansour, Egbert Molenkamp, Thijs Krol
ISCAS
2002
IEEE
190views Hardware» more  ISCAS 2002»
15 years 2 months ago
A high performance JPEG2000 architecture
—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of ...
Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
COMPSAC
2009
IEEE
15 years 2 months ago
Transaction Level Control for Application Execution on the SegBus Platform
Abstract—We define here a simple, low level control procedure definition, to support application implementation on a particular multiprocessor platform, namely the SegBus segme...
Tiberiu Seceleanu, Ivica Crnkovic, Cristina Cersch...
EUROMICRO
2000
IEEE
15 years 2 months ago
A Simulink(c)-Based Approach to System Level Design and Architecture Selection
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
Luciano Lavagno, Begoña Pino, Leonardo Mari...
ISSS
2000
IEEE
128views Hardware» more  ISSS 2000»
15 years 2 months ago
Hardware Synthesis from SPDF Representation for Multimedia Applications
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
Chanik Park, Soonhoi Ha