352 search results - page 54 / 71 » VHDL |
145
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EURODAC
1994
IEEE
15 years 8 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
150
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EURODAC
1994
IEEE
15 years 8 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
137
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EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses 8 , the algorithm of Krishnamurthy 13 , and Sanchis's extensions of these al...
162
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ICIP
2006
IEEE
16 years 6 months ago
2006
IEEE
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
148
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CHES
2009
Springer
16 years 5 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...