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VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
15 years 10 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
VLSID
2002
IEEE
132views VLSI» more  VLSID 2002»
15 years 10 months ago
VLSI Architecture for a Flexible Motion Estimation with Parameters
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsu...
ICCD
2002
IEEE
98views Hardware» more  ICCD 2002»
15 years 6 months ago
Parallel Multiple-Symbol Variable-Length Decoding
In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit buffer whose accumulated codelength ...
Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, M...
ICCAD
2001
IEEE
163views Hardware» more  ICCAD 2001»
15 years 6 months ago
Predicting the Performance of Synchronous Discrete Event Simulation Systems
In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cyc...
Jinsheng Xu, Moon-Jung Chung
90
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RTAS
2009
IEEE
15 years 4 months ago
The System-Level Simplex Architecture for Improved Real-Time Embedded System Safety
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...
Stanley Bak, Deepti K. Chivukula, Olugbemiga Adeku...