352 search results - page 8 / 71 » VHDL |
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
We present a rigorous but transparent semantic de nition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assi...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...
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INFORMATICALT
1998
14 years 9 months ago
1998
This paper describes a method how to represent and build a reusable VHDL component. By that component we can, for example, describe a family of the relative VHDL models. To represe...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
: This article describes the current state of the project to develop distributed simulation. The reader will have