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EURODAC
1994
IEEE
124views VHDL» more  EURODAC 1994»
15 years 1 months ago
Automotive databus simulation using VHDL
developed and standardised, for example CAN[1][2], J1850[3]. THE ELECTRONIC VEHICLE TODAYVHDL has been used to develop a simulator for automotive databus networks. This is a design...
Karen Hale
EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
15 years 1 months ago
VHDL quality: synthesizability, complexity and efficiency evaluation
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
M. Mastretti
EURODAC
1995
IEEE
153views VHDL» more  EURODAC 1995»
15 years 1 months ago
VHDL-based communication and synchronization synthesis
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level descripti...
Wolfgang Ecker, Manfred Huber
ITC
2003
IEEE
113views Hardware» more  ITC 2003»
15 years 2 months ago
Fault Injection for Verifying Testability at the VHDL Level
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
S. R. Seward, Parag K. Lala
BMAS
2000
IEEE
15 years 2 months ago
On Accommodating Particular Analog System Models with VHDL
In this paper the problem of accommodating particular analog system models, with emphasis on interconnection's representation, with discrete event simulators, and particularl...
Gabriel Stefan Popescu