70 search results - page 10 / 14 » VLSI Implementation of a Fault-Tolerant Distributed Clock Ge... |
90
Voted
ISCAS
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
GECCO
2009
Springer
15 years 4 months ago
2009
Springer
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
84
Voted
FCCM
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
71
Voted
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
SBCCI
2005
ACM
15 years 3 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...