70 search results - page 11 / 14 » VLSI Implementation of a Fault-Tolerant Distributed Clock Ge... |
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
ASAP
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
80
Voted
EMSOFT
2004
Springer
15 years 2 months ago
2004
Springer
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
FCCM
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
88
Voted
HPCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...