70 search results - page 9 / 14 » VLSI Implementation of a Fault-Tolerant Distributed Clock Ge... |
139
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BMCBI
2010
14 years 8 months ago
2010
Background: The Ensembl project produces updates to its comparative genomics resources with each of its several releases per year. During each release cycle approximately two week...
124
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VLSID
1997
IEEE
15 years 5 months ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
101
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DAC
2004
ACM
15 years 6 months ago
2004
ACM
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
111
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VLSID
2004
IEEE
16 years 1 months ago
2004
IEEE
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
104
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FCCM
2003
IEEE
15 years 6 months ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...