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160
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TSP
2008
158views more  TSP 2008»
15 years 3 months ago
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
Chao Cheng, Keshab K. Parhi
189
Voted
TIM
2010
294views Education» more  TIM 2010»
14 years 10 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
140
Voted
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
15 years 9 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
113
Voted
ICCAD
1994
IEEE
151views Hardware» more  ICCAD 1994»
15 years 7 months ago
Multi-way VLSI circuit partitioning based on dual net representation
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
Jason Cong, Wilburt Labio, Narayanan Shivakumar
149
Voted
DAC
2005
ACM
15 years 5 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey