2449 search results - page 112 / 490 » VLSI |
101
click to vote
ICC
2007
IEEE
15 years 10 months ago
2007
IEEE
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
154
click to vote
IJCNN
2007
IEEE
15 years 10 months ago
2007
IEEE
—The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35µm CMOS technology. The fir...
134
click to vote
ISCAS
2007
IEEE
15 years 10 months ago
2007
IEEE
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
152
click to vote
APCCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance...