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ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
15 years 9 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
BIOADIT
2004
Springer
15 years 9 months ago
Characterizing the Firing Properties of an Adaptive Analog VLSI Neuron
Daniel Ben Dayan Rubin, Elisabetta Chicca, Giacomo...
123
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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 9 months ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee
ISCAS
2003
IEEE
75views Hardware» more  ISCAS 2003»
15 years 9 months ago
VLSI implementation of a real-time video watermark embedder and detector
This paper describes the hardware design and implementation of the JAWS (Just Another Watermarking System) embedder and detector for watermarking of realtime uncompressed digital ...
Nebu John Muthui, Ali Sheikholeslami, Deepa Kundur