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    IEICET
    2007
    63views more  IEICET 2007»
    VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
    15 years 3 months ago
    VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
    Download  www.cs.nctu.edu.tw
    Lan-Da Van, Chin-Teng Lin, Yuan-Chu Yu
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    TVLSI
    2008
    133views more  TVLSI 2008»
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    15 years 3 months ago
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    Download  www.eecs.wsu.edu
    Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
    Mitchell J. Myjak, José G. Delgado-Frias
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    VLSISP
    2008
    102views more  VLSISP 2008»
    VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
    15 years 3 months ago
    VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
    Download  video.ee.ntu.edu.tw
    Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-We...
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    CONCURRENCY
    2000
    61views more  CONCURRENCY 2000»
    Parallel VLSI test in a shared-memory multiprocessor
    15 years 3 months ago
    Parallel VLSI test in a shared-memory multiprocessor
    Download  hera.ugr.es
    Consolación Gil, Julio Ortega, Maria Dolore...
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    IJNS
    2000
    130views more  IJNS 2000»
    A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems
    15 years 3 months ago
    A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems
    Download  www2.imse-cnm.csic.es
    An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
    Teresa Serrano-Gotarredona, Andreas G. Andreou, Be...
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