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89
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FCCM
2005
IEEE
113views VLSI» more  FCCM 2005»
15 years 9 months ago
A Comparison of Floating Point and Logarithmic Number Systems for FPGAs
Michael Haselman, Michael J. Beauchamp, Aaron Wood...
124
Voted
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 9 months ago
Parallelism/regularity-driven MIMO detection algorithm design
Efficient VLSI implementation of multiple-input multiple-output (MIMO) detectors plays an important role in the real-life implementation of MIMO communication systems. However, m...
Tong Zhang, Yan Xin, Sizhong Chen
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
15 years 9 months ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
15 years 9 months ago
Distributed neurochemical sensing: in vitro experiments
Experimental results characterizing a VLSI multi-channel potentiostat sensor system designed for sensing distributed neurotransmitter activity are presented. Neurotransmitter conc...
G. Mulliken, Mihir Naware, A. Bandyopadhyay, Gert ...