2449 search results - page 152 / 490 » VLSI |
114
Voted
DFT
2004
IEEE
15 years 7 months ago
2004
IEEE
We present a model for computing the probability of a parametric failure due to a spot defect. The analysis is based on electromigration in conductors under unidirectional current...
103
Voted
FCCM
2004
IEEE
15 years 7 months ago
2004
IEEE
ended abstract presents further results from the word-length optimization system Right-Size described at FCCM 2003. The system is used to quantify the compiletime specialization s...
115
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FCCM
2004
IEEE
15 years 7 months ago
2004
IEEE
This poster proposes a technique, based on polynomial approximation, which can be applied to convert ROMs into a combination of arithmetic operations and smaller ROMs. We show tha...
137
Voted
FCCM
1997
IEEE
15 years 7 months ago
1997
IEEE
In this paper we introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. Our performance estimate shows that ou...
152
Voted
EURODAC
1995
IEEE
15 years 7 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...