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FCCM
1995
IEEE
135views VLSI» more  FCCM 1995»
15 years 7 months ago
Architectural descriptions for FPGA circuits
FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description l...
Satnam Singh
128
Voted
GLVLSI
2010
IEEE
150views VLSI» more  GLVLSI 2010»
15 years 6 months ago
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM...
Anuj Pushkarna, Hamid Mahmoodi
ISPD
2007
ACM
86views Hardware» more  ISPD 2007»
15 years 5 months ago
Dummy fill density analysis with coupling constraints
In modern VLSI manufacturing processes, dummy fills are widely used to adjust local metal density in order to improve layout unifor
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao,...
GLVLSI
2008
IEEE
105views VLSI» more  GLVLSI 2008»
15 years 5 months ago
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
135
Voted
FCCM
2007
IEEE
168views VLSI» more  FCCM 2007»
15 years 4 months ago
Discrete-Time Cellular Neural Networks in FPGA
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
J. Javier Martínez-Álvarez, F. Javie...