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DFT
2002
IEEE
115views VLSI» more  DFT 2002»
15 years 9 months ago
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis
IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio o...
Sagar S. Sabade, D. M. H. Walker
FCCM
2002
IEEE
109views VLSI» more  FCCM 2002»
15 years 9 months ago
Compiling ATR Probing Codes for Execution on FPGA Hardware
This paper describes the implementation of an automatic target recognition ATR Probing algorithm on a recon gurable system, using the SA-C programming language and optimizing co...
A. P. Wim Böhm, J. Ross Beveridge, Bruce A. D...
FCCM
2002
IEEE
114views VLSI» more  FCCM 2002»
15 years 9 months ago
Implementing a Simple Continuous Speech Recognition System on an FPGA
Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. W...
Stephen J. Melnikoff, Steven F. Quigley, Martin J....
GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
15 years 9 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
ISVLSI
2002
IEEE
116views VLSI» more  ISVLSI 2002»
15 years 9 months ago
Multi-Output Timed Shannon Circuits
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
Mitchell A. Thornton, Rolf Drechsler, D. Michael M...