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VLSID
2002
IEEE
81views VLSI» more  VLSID 2002»
15 years 9 months ago
A New Synthesis of Symmetric Functions
A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this...
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattac...
DFT
2000
IEEE
104views VLSI» more  DFT 2000»
15 years 8 months ago
How Does Resource Utilization Affect Fault Tolerance?
Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of...
Andreas Steininger, Christoph Scherrer
GLVLSI
2000
IEEE
75views VLSI» more  GLVLSI 2000»
15 years 8 months ago
A wave-pipelined router architecture using ternary associative memory
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
José G. Delgado-Frias, Jabulani Nyathi, Lax...
GLVLSI
2000
IEEE
90views VLSI» more  GLVLSI 2000»
15 years 8 months ago
Low power high speed analog-to-digital converter for wireless communications
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
A. E. Hussein, Mohamed I. Elmasry
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
15 years 8 months ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome