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VLSID
1999
IEEE
87views VLSI» more  VLSID 1999»
15 years 8 months ago
Optimal Retiming for Initial State Computation
Retiming is a transformation that optimizes a sequential circuit by relocating the registers. When the circuit has an initial state, one must compute an equivalent initial state f...
Peichen Pan, Guohua Chen
DFT
1998
IEEE
94views VLSI» more  DFT 1998»
15 years 8 months ago
An Integrated HW and SW Fault Injection Environment for Real-Time Systems
This paper describes a system suited to support the Fault Injection process for microprocessor-based embedded systems. The system exploits a low-cost hardware board to monitor the...
Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza R...
DFT
1998
IEEE
78views VLSI» more  DFT 1998»
15 years 8 months ago
A System for Evaluating On-Line Testability at the RT-level
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda...
DFT
1998
IEEE
96views VLSI» more  DFT 1998»
15 years 8 months ago
A Systematic Approach for Diagnosing Multiple Delay Faults
In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach...
Jayabrata Ghosh-Dastidar, Nur A. Touba
FCCM
1998
IEEE
116views VLSI» more  FCCM 1998»
15 years 8 months ago
A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure
Abstract This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be emb...
Simon D. Haynes, Peter Y. K. Cheung